Cmos Logic Gate Generation and Optimization by Exploring Pre- Defined Switch Networks
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چکیده
This work investigates the Moore’s catalog of switch networks and its use to optimize the CMOS logic gate design. It presents an analysis of networks’ properties described in the catalog, as the number of switches, the series-parallel associations in the arrangements, the longest device path, the planar profile of the network, and so on. The approach used to generate such data is shown as well as some experimental results illustrating the usefulness of this catalog. Moreover, the Moore’s catalog has been verified and validated by such computational analysis.
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تاریخ انتشار 2011